Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial $180$ nm HV-CMOS process and contains a matrix of $128\times128$ square pixels with $25$ $\mu$m pitch. First prototypes have been produced with a standard resistivity of $\sim20$ $\Omega$cm for the substrate and tested in standalone mode. The results show a rise time of $\sim20$ ns, charge gain of $190$ mV/ke$^{-}$ and $\sim40$ e$^{-}$ RMS noise for a power consumption of $4.8$ $\mu$W/pixel. The main design aspects, as well as standalone measurement results, are presented.Comment: 13 pages, 13 figures, 2 tables. Work carried out in the framework of the CLICdp collaboratio

CliCTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker

The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a 180 nm imaging CMOS process built on a high-resistivity epitaxial layer. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of 16 x 128 elongated pixels, each measuring 300 x 30 μm$^{2}$. To ensure prompt charge collection, every elongated pixel is segmented in eight sub-pixels, each containing a collection diode and a separate analog front-end. A simultaneous 8-bit time measurement with 10 ns time bins and 5-bit energy measurement with programmable range is performed in the on-pixel digital logic. The main design aspects as well as the first results from laboratory measurements with the CLICTD chip are presented

Design and characterisation of the CLICTD pixelated monolithic sensor chip

A novel monolithic pixelated sensor and readout chip, the CLIC Tracker Detector (CLICTD) chip, is presented. The CLICTD chip was designed targeting the requirements of the silicon tracker development for the experiment at the Compact Linear Collider (CLIC), and has been fabricated in a modified 180 nm CMOS imaging process with charge collection on a high-resistivity p-type epitaxial layer. The chip features a matrix of 16×128 elongated channels, each measuring 300×30 μm2. Each channel contains 8 equidistant collection electrodes and analog readout circuits to ensure prompt signal formation. A simultaneous 8-bit Time-of-Arrival (with 10 ns time bins) and 5-bit Time-over-Threshold measurement is performed on the combined digital output of the 8 sub-pixels in every channel. The chip has been fabricated in two process variants and characterised in laboratory measurements using electrical test pulses and radiation sources. Results show a minimum threshold between 135 and 180 e‾ and a noise of about 14 e‾ RMS. The design aspects and characterisation results of the CLICTD chip are presented

Detector Technologies for CLIC

The Compact Linear Collider (CLIC) is a high-energy high-luminosity linear electron-positron collider under development. It is foreseen to be built and operated in three stages, at centre-of-mass energies of 380 GeV, 1.5 TeV and 3 TeV, respectively. It offers a rich physics program including direct searches as well as the probing of new physics through a broad set of precision measurements of Standard Model processes, particularly in the Higgs-boson and top-quark sectors. The precision required for such measurements and the specific conditions imposed by the beam dimensions and time structure put strict requirements on the detector design and technology. This includes low-mass vertexing and tracking systems with small cells, highly granular imaging calorimeters, as well as a precise hit-time resolution and power-pulsed operation for all subsystems. A conceptual design for the CLIC detector system was published in 2012. Since then, ambitious R&D programmes for silicon vertex and tracking detectors, as well as for calorimeters have been pursued within the CLICdp, CALICE and FCAL collaborations, addressing the challenging detector requirements with innovative technologies. This report introduces the experimental environment and detector requirements at CLIC and reviews the current status and future plans for detector technology R&D.Comment: 152 pages, 116 figures; published as CERN Yellow Report Monograph Vol. 1/2019; corresponding editors: Dominik Dannheim, Katja Kr\"uger, Aharon Levy, Andreas N\"urnberg, Eva Sickin

The Compact Linear Collider (CLIC) - 2018 Summary Report

The Compact Linear Collider (CLIC) is a TeV-scale high-luminosity linear $e^+e^-$ collider under development at CERN. Following the CLIC conceptual design published in 2012, this report provides an overview of the CLIC project, its current status, and future developments. It presents the CLIC physics potential and reports on design, technology, and implementation aspects of the accelerator and the detector. CLIC is foreseen to be built and operated in stages, at centre-of-mass energies of 380 GeV, 1.5 TeV and 3 TeV, respectively. CLIC uses a two-beam acceleration scheme, in which 12 GHz accelerating structures are powered via a high-current drive beam. For the first stage, an alternative with X-band klystron powering is also considered. CLIC accelerator optimisation, technical developments and system tests have resulted in an increased energy efficiency (power around 170 MW) for the 380 GeV stage, together with a reduced cost estimate at the level of 6 billion CHF. The detector concept has been refined using improved software tools. Significant progress has been made on detector technology developments for the tracking and calorimetry systems. A wide range of CLIC physics studies has been conducted, both through full detector simulations and parametric studies, together providing a broad overview of the CLIC physics potential. Each of the three energy stages adds cornerstones of the full CLIC physics programme, such as Higgs width and couplings, top-quark properties, Higgs self-coupling, direct searches, and many precision electroweak measurements. The interpretation of the combined results gives crucial and accurate insight into new physics, largely complementary to LHC and HL-LHC. The construction of the first CLIC energy stage could start by 2026. First beams would be available by 2035, marking the beginning of a broad CLIC physics programme spanning 25-30 years

Verification methodology of a multi-mode radiation-hard high-speed transceiver ASIC

The second version of Low Power Giga Bit Transceiver (lpGBTv1) addresses the functional and radiation-related issues discovered during the testing of lpGBTv0 prototype. Considerable changes to the chip configuration architecture and flow were required. The Universal Verification Methodology (UVM) based verification environment was extensively refactored to address the functional verification challenges posed by the architectural changes in the chip. Additionally, the new UVM environment was designed to support extensive verification of robustness to Single Event Effects (SEE). In this paper we present the revamped UVM verification framework of lpGBTv1 and discuss the verification process, tools, techniques and metrics used to sign-off the design before submission

CLICTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker

The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a $180$ nm imaging CMOS process built on a high-resistivity epitaxial layer. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of ${16\times128}$ elongated pixels, each measuring ${300\times30}$ $\mu$m$^2$. To ensure prompt charge collection, every elongated pixel is segmented in eight sub-pixels, each containing a collection diode and a separate analog front-end. A simultaneous $8$-bit time measurement with $10$ ns time bins and $5$-bit energy measurement with programmable range is performed in the on-pixel digital logic. The main design aspects as well as the first results from laboratory measurements with the CLICTD chip are presented.The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a 180 nm imaging CMOS process built on a high-resistivity epitaxial layer. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of 16 × 128 elongated pixels, each measuring 300 × 30 μm$^2$. To ensure prompt charge collection, every elongated pixel is segmented in eight sub-pixels, each containing a collection diode and a separate analog front-end. A simultaneous 8-bit time measurement with 10 ns time bins and 5-bit energy measurement with programmable range is performed in the on-pixel digital logic. The main design aspects as well as the first results from laboratory measurements with the CLICTD chip are presented